Counters - General Questions (6)

In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?

The hexadecimal equivalent of 15,536 is ________.

The terminal count of a 3-bit binary counter in the DOWN mode is ________.

A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________.

A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse?

The final output of a modulus-8 counter occurs one time for every ________.

An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?

Three cascaded modulus-5 counters have an overall modulus of ________.