In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?

[A].	A trigger edge has occurred and we must load the counter.
[B].	The counter is zero and we need to keep it at zero.
[C].	The shift register is reset.
[D].	The counter is not zero and we need to count down by one.

Answer: Option C

Explanation:

No answer description available for this question