Counters - General Questions (7)

Directions to Solve

Counters - General Questions

49.

Which of the following procedures could be used to check the parallel loading feature of a counter?

A.	Preset the LOAD inputs, set the CLR to its active level, and check to see that the Q outputs match the values preset into the LOAD inputs.
B.	Apply LOWs to the parallel DATA inputs, pulse the CLK input, and check for LOWs on all the Q outputs.
C.	Apply HIGHs to all the DATA inputs, pulse the CLK and CLR inputs, and check to be sure that the Q outputs are all LOW.
D.	Apply HIGHs to all the Q terminals, pulse the CLK, and check to see if the DATA terminals now match the Q outputs.

Answer: Option B

Explanation:

No answer description available for this question.

50.

A four-channel scope is used to check the counter in the figure given below. Are the displayed waveforms correct?

mcq7_1012_1

A.	Yes
B.	No

Answer: Option B

Explanation:

No answer description available for this question

51.

A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (t_p(tot)) is ________.

A.	12 ms
B.	24 ns
C.	48 ns
D.	60 ns

Answer: Option D

Explanation:

No answer description available for this question

52.

How many different states does a 3-bit asynchronous counter have?

A.	2
B.	4
C.	8
D.	16

Answer: Option C

Explanation:

No answer description available for this question

53.

Which of the following is an invalid output state for an 8421 BCD counter?

A.	1110
B.	0000
C.	0010
D.	0001

Answer: Option A

Explanation:

No answer description available for this question.

54.

For a multistage counter to be truly synchronous, the ________ of each stage must be connected to ________.

A.	Cp, the same clock input line
B.	CE, the same clock input line
C.	, the terminal count output
D.	both clock input lines

Answer: Option A

Explanation:

No answer description available for this question

55.

Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.

A.	When MR1 and MR2 are both HIGH, all Qs will be reset to zero.
B.	When MR1 and MR2 are both HIGH, all Qs will be reset to one.
C.	MR1 and MR2 are provided to synchronously reset all four flip-flops.
D.	To enable the count mode, MR1 and MR2 must be held LOW.

Answer: Option A

Explanation:

No answer description available for this question

56.

The process of designing a synchronous counter that will count in a nonbinary manner is primarily based on:

A.	external logic circuits that decode the various states of the counter to apply the correct logic levels to the J-K inputs
B.	modifying BCD counters to change states on every second input clock pulse
C.	modifying asynchronous counters to change states on every second input clock pulse
D.	elimination of the counter stages and the addition of combinational logic circuits to produce the desired counts

Answer: Option A

Explanation:

No answer description available for this question

Counters - General Questions (7)

Counters - General Questions

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