The carry propagation delay in full-adder circuits:

[A].	is normally not a consideration because the delays are usually in the nanosecond range.
[B].	decreases in a direct ratio to the total number of FA stages.
[C].	is cumulative for each stage and limits the speed at which arithmetic operations are performed.
[D].	increases in a direct ratio to the total number of FA stages but is not a factor in limiting the speed of arithmetic operations.

Answer: Option C

Explanation:

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