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Shift Registers - General Questions

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Shift Registers - General Questions

1. 

When the output of a tristate shift register is disabled, the output level is placed in a:

A. float state
B. LOW state
C. high-impedance state
D. float or high-impedance state

Answer: Option D

Explanation:

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2. 

How much storage capacity does each stage in a shift register represent?

A. One bit
B. Two bits
C. Four bits (one nibble)
D. Eight bits (one byte)

Answer: Option A

Explanation:

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3. 

If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?

A. 1101000000
B. 0011010000
C. 1100000000
D. 0000000000

Answer: Option B

Explanation:

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4. 

In a 4-bit Johnson counter sequence there are a total of how many states, or bit patterns?

A. 1
B. 2
C. 4
D. 8

Answer: Option D

Explanation:

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5. 

Computers operate on data internally in a ________ format.

A. tristate
B. universal
C. parallel
D. serial

Answer: Option C

Explanation:

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6. 

To serially shift a nibble (four bits) of data into a shift register, there must be ________.

A. one clock pulse
B. four clock pulses
C. eight clock pulses
D. one clock pulse for each 1 in the data

Answer: Option B

Explanation:

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7. 

Another way to connect devices to a shared data bus is to use a ________.

A. circulating gate
B. transceiver
C. bidirectional encoder
D. strobed latch

Answer: Option B

Explanation:

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8. 

With a 50 kHz clock frequency, six bits can be serially entered into a shift register in ________.

A. 12 mu (3)
B. 120 mu (3)
C. 12 ms
D. 120 ms

Answer: Option B

Explanation:

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