Digital Design - General Questions

Directions to Solve

Digital Design - General Questions

1.

One example for the use of a Schmitt trigger is as a(n):

A.	switch debouncer
B.	racer
C.	astable oscillator
D.	transition pulse generator

Answer: Option A

Explanation:

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2.

Decoupling capacitors should be tied from V_CC on one device to ground on a different device.

A.	True
B.	False

Answer: Option B

Explanation:

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3.

What is the major advantage of the J-K flip-flop over the S-R flip-flop?

A.	The J-K flip-flop is much faster.
B.	The J-K flip-flop does not have propagation delay problems.
C.	The J-K flip-flop has a toggle state.
D.	The J-K flip-flop has two outputs.

Answer: Option C

Explanation:

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4.

Why should a LED be pulled LOW from a logic gate rather than pulled HIGH?

A.	LOW-level current is smaller.
B.	LOW-level current is larger.
C.	HIGH-level current is larger.
D.	LOW-level current is smaller and HIGH-level current is larger.

Answer: Option B

Explanation:

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5.

How much setup time (t_s) is required for the 74LS76?

A.	5 ns
B.	10 ns
C.	20 ns
D.	40 ns

Answer: Option C

Explanation:

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6.

Which of the following flip-flop timing parameters indicates the time it takes a Q output to respond to a C_p input?

A.	ts, th
B.	tPHL, tPLH
C.	tw (L), tw (H)
D.	fmax

Answer: Option B

Explanation:

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7.

Define a race condition for a flip-flop.

A.	The inputs to a trigger device are changing slightly before the active trigger edge.
B.	The inputs to a trigger device are changing slightly after the active trigger edge.
C.	The inputs to a trigger device are changing at the same time as the active trigger edge.

Answer: Option C

Explanation:

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8.

What is the difference between setup time and hold time?

A.	Setup time occurs after the active clock edge, hold time occurs before the active clock edge.
B.	Setup time occurs before the active clock edge, hold time occurs after the active clock edge.
C.	Setup time and hold time both occur at the active clock edge.

Answer: Option B

Explanation:

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