Digital System Projects Using HDL - General Questions

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Digital System Projects Using HDL - General Questions

1.

For the frequency counter, which is not a control signal from the control and timing block?

A.	Clear
B.	Enable
C.	Reset
D.	Store

Answer: Option C

Explanation:

No answer description available for this question.

2.

In the keypad application, just after the 4 ms mark the simulation imitates the release of the key by changing the column value back to F hex, which causes the d output to go into its Hi-Z state. On the next rising clock edge, what happens to dav?

A.	It goes HIGH.
B.	It goes LOW.
C.	It goes to Hi-Z.
D.	It goes to 1111H.

Answer: Option B

Explanation:

No answer description available for this question.

3.

When designing an HDL digital system, which is the worst mistake one can make?

A.	Concluding that a fundamental block works perfectly
B.	Failing to provide proper documentation
C.	Adding blocks of code prior to testing them
D.	Overlooking a possible VARIABLE

Answer: Option A

Explanation:

No answer description available for this question.

4.

List three basic blocks in the digital clock project.

A.	MOD-60, MOD-12 counters
B.	MOD-5, MOD-10, MOD-12 counters
C.	MOD-60, MOD-10 counters
D.	MOD-6, MOD-12, and MOD-10 counters

Answer: Option D

Explanation:

No answer description available for this question.

5.

In the frequency counter, what is the function of the Schmitt trigger circuit?

A.	To reduce input noise
B.	To condition the input signal
C.	To convert non-square waveforms
D.	To provide a usable signal to the display unit

Answer: Option C

Explanation:

No answer description available for this question.

6.

In the keypad application, when all columns are HIGH, the ring counter is enabled and counting, and dav is LOW, what is the status of the d outputs?

A.	On
B.	Off
C.	Hi-Z
D.	1011

Answer: Option C

Explanation:

No answer description available for this question.

7.

In the digital clock project, what type of counter is used to count to 59 seconds?

A.	MOD-60
B.	MOD-6
C.	BCD
D.	BCD followed by a MOD-6

Answer: Option D

Explanation:

No answer description available for this question.

8.

What are two ways to remember the current state of a counter in VHDL?

A.	With FUNCTIONS and PROCESS
B.	With counters and timers
C.	With SIGNAL and VARIABLE
D.	With bit types

Answer: Option C

Explanation:

No answer description available for this question.

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