Flip-Flops - General Questions (2)

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Flip-Flops - General Questions

If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?

A.	invalid
B.	No change will occur in the output.
C.	The output will toggle.
D.	output

Answer: Option B

Explanation:

No answer description available for this question

10.

The output pulse width of a 555 monostable circuit with R₁ = 4.7 k omega (6) and C₁ = 47 mu (4) F is ________.

A.	24 s
B.	24 ms
C.	243 ms
D.	243 s

Answer: Option C

Explanation:

No answer description available for this question

11.

A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what could be causing the problem?

mcq5_1015_2

A.	The output is always low; the circuit is defective.
B.	The Q output should be the complement of the short][show_qimage 2507][/short] output; the S and R terminals are reversed.
C.	The Q should be following the R input; the R input is defective.
D.	There is nothing wrong with the circuit.

Answer: Option A

Explanation:

No answer description available for this question

12.

In VHDL, in which declaration section is a COMPONENT declared?

A.	Architecture
B.	Library
C.	Entity
D.	Port map

Answer: Option A

Explanation:

No answer description available for this question

13.

The output of a gated S-R flip-flop changes only if the:

A.	flip-flop is set
B.	control input data has changed
C.	flip-flop is reset
D.	input data has no change

Answer: Option B

Explanation:

No answer description available for this question

14.

In VHDL, how is each instance of a component addressed?

A.	A name followed by a colon and the name of the library primitive
B.	A name followed by a semicolon and the component type
C.	A name followed by the library being used
D.	A name followed by the component library number

Answer: Option A

Explanation:

No answer description available for this question

15.

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

A.	cross coupling
B.	gate impedance
C.	low input voltages
D.	asynchronous operation

Answer: Option A

Explanation:

No answer description available for this question

16.

Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.

A.	00
B.	11
C.	01
D.	10

Answer: Option A

Explanation:

No answer description available for this question

Flip-Flops - General Questions (2)

Flip-Flops - General Questions

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