Flip-Flops - General Questions (3)

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Flip-Flops - General Questions

17.

Which is not a real advantage of HDL?

A.	Using higher levels of abstraction
B.	Tailoring components to exactly fit the needs of the project
C.	The use of graphical tools
D.	Using higher levels of abstraction and tailoring components to exactly fit the needs of the project

Answer: Option C

Explanation:

No answer description available for this question.

18.

Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.

A.	True
B.	False

Answer: Option B

Explanation:

No answer description available for this question

19.

A 555 operating as a monostable multivibrator has a C₁ = 100 mu (4) F. Determine R₁ for a pulse width of 500 ms.

A.	45
B.	455
C.	4.5 k
D.	455 k

Answer: Option C

Explanation:

No answer description available for this question

20.

A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?

A.	The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being used.
B.	The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of the terminals to correct the problem.
C.	A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a NAND gate.
D.	A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop.

Answer: Option D

Explanation:

No answer description available for this question

21.

If an input is activated by a signal transition, it is ________.

A.	edge-triggered
B.	toggle triggered
C.	clock triggered
D.	noise triggered

Answer: Option A

Explanation:

No answer description available for this question

22.

A positive edge-triggered D flip-flop will store a 1 when ________.

A.	the D input is HIGH and the clock transitions from HIGH to LOW
B.	the D input is HIGH and the clock transitions from LOW to HIGH
C.	the D input is HIGH and the clock is LOW
D.	the D input is HIGH and the clock is HIGH

Answer: Option B

Explanation:

No answer description available for this question

23.

As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:

A.	very long.
B.	very short.
C.	at a maximum value to enable the input control signals to stabilize.
D.	of no consequence as long as the levels are within the determinate range of value.

Answer: Option B

Explanation:

No answer description available for this question.

24.

Edge-triggered flip-flops must have:

A.	very fast response times.
B.	at least two inputs to handle rising and falling edges.
C.	a pulse transition detector.
D.	active-LOW inputs and complemented outputs.

Answer: Option C

Explanation:

No answer description available for this question

Flip-Flops - General Questions (3)

Flip-Flops - General Questions

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