Flip-Flops - General Questions (10)

Directions to Solve

73.

How many flip-flops are in the 7475 IC?

Answer: Option B

Explanation:

No answer description available for this question.

74.

How is a J-K flip-flop made to toggle?

Answer: Option D

Explanation:

No answer description available for this question.

75.

Propagation delay time, t_PLH, is measured from the ________.

A.	triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
B.	triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
C.	preset input to the LOW-to-HIGH transition of the output
D.	clear input to the HIGH-to-LOW transition of the output

Answer: Option A

Explanation:

No answer description available for this question

76.

Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?

A.	The logic level at the D input is transferred to Q on NGT of CLK.
B.	The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
C.	The Q output is ALWAYS identical to the D input when CLK = PGT.
D.	The Q output is ALWAYS identical to the D input.

Answer: Option A

Explanation:

No answer description available for this question

77.

Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.

Answer: Option B

Explanation:

No answer description available for this question