Shift Registers - General Questions (5)

How would a latch circuit be used in a microprocessor system?

If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse?

The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses?

A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (t_d) of ________.

With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________.

A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________.

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)