Integrated-Circuit Logic Families - General Questions (4)

Directions to Solve

Integrated-Circuit Logic Families - General Questions

25.

Which of the following summarizes the important features of ECL?

A.	Low noise margin, low output voltage swing, negative voltage operation, fast, and high power consumption
B.	Good noise immunity, negative logic, high frequency capability, low power dissipation, and short propagation time
C.	Slow propagation time, high frequency response, low power consumption, and high output voltage swings
D.	Poor noise immunity, positive supply voltage operation, good low frequency operation, and low power

Answer: Option A

Explanation:

No answer description available for this question.

26.

Which of the following logic families has the shortest propagation delay?

A.	S-TTL
B.	AS-TTL
C.	HS-TTL
D.	HCMOS

Answer: Option B

Explanation:

No answer description available for this question.

27.

Which of the following will not normally be found on a data sheet?

A.	Minimum HIGH level output voltage
B.	Maximum LOW level output voltage
C.	Minimum LOW level output voltage
D.	Maximum HIGH level input current

Answer: Option C

Explanation:

No answer description available for this question.

28.

Logic circuits that are designated as buffers, drivers, or buffer/drivers are designed to have:

A.	a greater current/voltage capability than an ordinary logic circuit.
B.	greater input current/voltage capability than an ordinary logic circuit.
C.	a smaller output current/voltage capability than an ordinary logic.
D.	greater input and output current/voltage capability than an ordinary logic circuit.

Answer: Option A

Explanation:

No answer description available for this question.

29.

Why is the fan-out of CMOS gates frequency dependent?

A.	Each CMOS input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a CMOS gate.
B.	When the frequency reaches the critical value, the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will be one-half of normal; this defines the upper operating frequency.
C.	The higher the number of gates attached to the output, the more frequently they will have to be serviced, thus reducing the frequency at which each will be serviced with an input signal.
D.	The input gates of the FETs are predominantly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the number of loads that may be attached to the output of the driving gate.

Answer: Option D

Explanation:

No answer description available for this question.

30.

Which of the following logic families has the highest maximum clock frequency?

A.	S-TTL
B.	AS-TTL
C.	HS-TTL
D.	HCMOS

Answer: Option B

Explanation:

No answer description available for this question.

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